In manufacturing IC (integrated circuit) devices, circuit net listing CAD (computer aided design) data and mask layout CAD data are generally used for automatically determining the mask layout including the wiring pattern in an IC device.
To evaluate a prototype IC device by, for example, locating defective points in the IC device which is experimentally produced, the circuit net listing CAD data and the mask layout CAD data that have been established and used for the production of the IC are formerly used. In such a conventional method, a defective point is specified with reference to a current or voltage waveform in each circuit component of the IC device by determining an interrelationship between the circuit net listing and the mask layout based on the CAD data.
The applicant of this invention disclosed an IC fault analysis display device of this kind in the Japanese Patent Application Serial number 1993-184,055, which is the prior art of this invention. A simplified block diagram of the IC fault analysis display device in the patent application is shown in FIG. 3.
In FIG. 3, the IC fault analysis display device 20 is connected with memory devices 10, 11 and 12 each of which is a floppy disk or hard disk or other kind of memory device. The IC fault analysis display device 20 is also connected to an input means 13 and an IC internal circuit analysis device 40.
The circuit net listing CAD data that has been used in the production of the IC is loaded in the outside memory device 10. The mask layout CAD data that has been used in the production stage is loaded in the outside memory device 11. Pin input-output attribute information is loaded in the outside memory device 12. Since the pin input-output attribute information is fixed data as will be described later, it can be stored in a memory device provided inside of the IC fault analysis display device 20.
The data read out from these outside memory devices 10, 11 and 12 are input to the IC fault analysis display device 20 having a computer therein. The IC fault analysis display device 20 comprises a net list data conversion part 21, a mask layout data conversion part 22, a net list vs. mask layout comparison part 23, a net list-circuit diagram generation part 24, a circuit diagram vs. mask layout comparison part 25, a net list data memory 26, a circuit diagram data memory 27, a mask layout data memory 28, a comparison data memory 29, a net list display 30, a circuit diagram display 31, and a mask layout display 32.
The net list data conversion part 21 and the mask layout data conversation part 22 respectively convert the format of the net listing CAD data and the mask layout CAD data to a format acceptable to the IC fault analysis display device 20.
The net listing data and the mask layout data that were converted to the net list data conversion part 21 and the mask layout data conversion part 22 are stored in the net list data memory 26 and the mask layout data memory 28, respectively. Then, each information in the net listing data is compared with the corresponding information in the mask layout data by the net list vs. mask layout comparison part 23.
The pin input-output attribute information from the memory 12 is input to the net list-circuit diagram generation part 24. The net list-circuit diagram generation part 24 generates a circuit diagram based on the pin input-output attribute information and the net listing data from the net list data conversion part 21.
In the IC fault analysis display device of FIG. 3, the pin input-output attribute information includes various names showing the kinds of elements provided in the IC device and also the names of terminals in the IC device. For example, R designates a resistor, L is an inductance, D is a diode, AND21 is AND gate of two inputs and one output. Other names indicating the kinds of elements like, C, J, V, I, Q, P, N and NAND are also included.
As for the name of the terminals of each element, in the case of C resistor R for example, the first pin is designated by A indicating an input terminal and the second pin is designated by Z indicating an output terminal. In the case of a junction field effect transistor J, the first pin is designated by G which indicates a gate terminal, the second pin designated by S indicating a source terminal, and the third pin is D indicating a drain terminal. Thus, by identifying a pin input-output attribute of each element, the net list-circuit diagram generation part 24 can read out a diagram pattern of each element and define each terminal of the element in the diagram pattern.
Namely, from a net listing shown in FIG. 4, a circuit diagram shown in FIG. 5 can be depicted. As in FIGS. 4 and 5, the cell number X1, for example, is a two-input-one-output AND gate having two input terminals A and B connected to the wirings IN1 and IN2, respectively, and one output terminal Z connected to the wiring OUT1. The cell number X2 is also a two-input-one-output AND gate having two input terminals A and B connected to the wirings IN3 and IN4, respectively, and one output terminal Z connected to the wiring OUT2. The cell X3 is a two-input-one-output NAND gate and has a first input terminal A connected to the wiring OUT1 and a second input terminal B connected to the wiring OUT2 and an output terminal Z connected to the wiring OUT3.
As soon as the circuit diagram data that has been generated in this way is stored in the circuit diagram data memory 27, the circuit diagram data is compared with the mask layout data and the net listing data by the circuit diagram vs. mask layout comparison part 25 to find out the corresponding points in the data. The corresponding circuit diagram, the mask layout and the net listing which indicate the same part of the IC device thus determined by the circuit diagram vs. mask layout comparison part 25 are illustrated on each of the displays 31, 32 and 30. The comparison data memory 29 stores the comparison data from the comparison part 25.
After storing all the circuit diagram data in the circuit diagram memory 27, the diagram display 31 displays the overall circuit diagram by selecting the functions indicated on an initial menu screen. An input means 13, such as a mouse, is used for identifying the specific position in the overall circuit diagram to be analyzed. The circuit diagram thus identified will be disclosed on the circuit diagram display 31 as shown in FIG. 6. In addition to the circuit diagram display, the net list and the mask layout are also displayed simultaneously on the display device 20 based on a multi-task function as shown in FIG. 6.
Therefore, by selecting the point of the IC to be analyzed in the circuit diagram shown in the circuit diagram display part 31, the comparison data memory 29 sends a control signal to the net list display 30 and the mask layout display 32 so that the net list and the mask layout corresponding to the selected point in the circuit diagram are displayed on the net list display 30 and the mask layout display 32. Furthermore, a particular wiring in the selected point can be highlighted on the net list display and the mask layout display by identifying such wiring through the input means 13. Such highlighting can be accomplished by brightening or flickering the selected wiring on the displays.
The selection of the specific part of the IC device for evaluation through the input means 13 can be performed not only on the circuit diagram display 31 but also on the net list display 30 or the mask layout display 32. Also, by designating the special part in either of the displays, it can be constituted that such a specific point and the points corresponding to the specific point can be indicated with flickers, brightened illustrations or bold lines on the displays 30, 31 and 32.
Further, the positional information included in the mask layout data is provided to the IC internal circuit analysis device 40 from the mask layout display 32. The IC internal circuit analysis device 40 analyzes the inside points of the IC device corresponding to the selected point on the circuit diagram. One of the examples of the IC internal circuit analysis device is a device formed of a charged particle beam tester such as an electron beam tester (EB tester) or an ion beam tester. The other type of the IC inside analysis device is formed of a optical microscope.
For example, in the charged particle beam tester, the IC device to be tested is arranged in a vacuum chamber of the beam tester. The charged particle beam is irradiated from the beam generator of the tester and the irradiated beam is scanned on the predetermined area of the IC device under test. As a result, the charged beam causes the emission of secondary electrons from the IC device under test, the amount of which is dependent upon the electric potential of a circuit point of the IC device receiving the beam. The amount of the secondary electron that occurs by the charged beam irradiation is measured in the form of an electric signal for every irradiation point in the IC device.
The measured data is processed by the charged particle beam tester so that a potential contrast image (SEM image: Scanning Electron Microscope image or SIM image: Scanning Ion Microscope image) and waveform data for the inside of the IC are formed. The potential contrast image data and the waveform image data are stored in a contrast image data memory and a waveform data memory (not shown), respectively. The potential contrast image and the waveform image of the specified location of the IC device are displayed on a display screen incorporated in the IC internal circuit analysis device 40.
The positional information provided to the IC internal circuit analysis device 40 from the mask layout display 32 includes X-Y coordinate data for identifying a position in the IC device and magnification data for indicating a size of an area in the IC device. Each irradiated position of the IC device under test can be designated by this positional information.
However, due to an inaccuracy occurred during the IC production or in the IC internal circuit analysis device, the mask layout data from the mask layout 32 and the potential contrast image do not completely match with each other. Therefore, in the conventional device of FIG. 3, a user has to fine-tune the X, Y coordinate positions of the IC device under test by comparing the mask layout and the observed contrast image. After completely adjusting the positions between the mask layout and the contrast image in the IC internal circuit analysis device 40, the evaluation of the IC under test is performed by monitoring the potential contrast image and the waveform displayed on the screen of the analysis device 40.
As described above, in the conventional IC defective analysis device of FIG. 3, the IC fault analysis display device 20 that analyzes information that obtained from CAD data for IC production and the IC internal circuit analysis device 40, which is typically on electron beam tester, do not suitably match with each other. This is because the conventional IC fault analysis system such as shown in FIG. 3 does not have means to correct the positional differences between the CAD data and the measured data obtained by IC internal circuit analysis device 40. Therefore, the interface between the two devices is not well established. For example, the exchange of data between the two devices was insufficient.
Therefore, it is difficult to establish correlationship between the mask layout or the net listing and the observed contrast image or the waveform image on the displays. The user has to input net names through a keyboard one by one for each contrast image and the waveform image displayed in the analysis device 40 corresponding to the selected portion of the IC device. Alternatively, the user has to take a memo or record a note in a print showing such images. Thus, in the conventional device, it is time consuming and tedious to determine the correlationship between the CAD data and the images in the beam tester.
Further, in the conventional device, the information flow between the IC fault analysis display device 20 and the IC internal circuit analysis device 40 is one-way, i.e., data transmission of the CAD data from the IC fault analysis display device to the IC internal circuit analysis device. Namely, there is no information flow from the charged beam tester 40 to the fault display device 20. However, in the practice of evaluating the IC devices, a user may discover the defective points of the IC device by observing the contrast image and the waveform image obtained in the charged particle beam tester. In such a case, a defective point found in the potential contrast image must be estimated its position by observing the mask layout display and the circuit diagram and then the accurate position of such defective point has to be confirmed by sending the mask layout data of the estimated position to the charged beam tester. This process in the conventional device is complicated, inconvenient and time consuming.